Document Summaries

Analog/Mixed-Signal VSI Extension Specification
Version 1 2.2 (AMS 1 2.2)
Analog/Mixed-Signal DWG
Revision Date: February 2001
Released November 1999

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This document specifies the exchange of Analog/Mixed-Signal virtual components (VCs) by defining the deliverables, their associated design guidelines, and data formats to facilitate the test, exchange, and integration of process-specific ("hard") mixed-signal virtual components targeting digital system-chip applications, such as A/D, D/A converters and PLLs.

Analog/Mixed-Signal Signal Integrity VSI Extension Specification
Version 1.0 (AMS 2 1.0)
Analog/Mixed-Signal DWG
Revision Date: March 2002
Released March 2002

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This document specifies and explains the deliverables, data formats, associated design guidelines, and example designs for the signal integrity issues of both digital and analog mixed-signal virtual components in SoC design.

On-Chip Bus Attributes Specification
Version 1 (OCB 1 2.0)
On-Chip Bus DWG
Revision Date: September 2001
Released August 1998

According to an agreement between VSIA and OCP International Partnership, OCP-IP has assumed stewardship of these specifications. For information about the VSIA OCB spec, please send an email to the OCP-IP organization at: admin@ocpip.org.

Signal Integrity Specification
Version 1 (IMP 12.0)
SI Sub-DWG of the Implementatoin DWG
Released January 2004

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Signal Integrity Specification (IMP 1 2.0) outlines the deliverables, data formats, associated design guidelines and example designs for SI issues of both digital and analog mixed-signal virtual components in SoCs.

Soft and Hard VC Structural, Performance and Physical Modeling Specification
Version 2.1 (I/V 1 2.1)
Implementation/Verification DWG
Revision Date: January 2001
Released May 1999

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This specification defines the data formats and the list of deliverables that should be used for structural, performance and physical modeling of both soft and hard VCs. The I/V specification includes the RTL source and performance model formats needed for both hard and soft VCs, summary of the design constraints requirements, endorsement of the OVI Design Constraints Working Group (DC-WG) for the development of the design constraints standard, and the endorsement of the Open Library (OLA) standard for the performance modeling standard.

The specification includes the data formats that should be used for the structural netlist and a number of physical data types associated with hard VCs.

VC/SoC Functional Verification Specification
Version 1 (VER 21.0)
Functional Verification DWG
Released March 2004

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The purpose of this specification is to define a number of common verification approaches, and to indicate how their use by a VC provider could be understood, or even reproduced, by a VC integrator. This specification facilitates the reuse of as much as possible of the verification environment delivered by the VC provider, by the end user, in the integration and chip-level verification of the end product. The verification environment comprises testbenches, models, scripts and other deliverables that are discussed in detail.

Test Data Interchange Formats and Guidelines for VC Providers Specification
Version 1 (TST 1 1.1)
Manufacturing Related Test DWG
Revision Date: January 2001
Released June 1999

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This specification covers Test Data Interchange formats and Design-For-Test (DFT) guidelines for VC Providers. Its purpose is to define the nature and format of the information transferred between the VC Provider and the VC Integrator. Guidelines for VC Providers are also presented, to insure successful incorporation of Virtual Components (VCs) into a system chip design using the VSIA (Virtual Socket Interface Alliance) methodology. All test-related information from the VSIA Architecture document (including Section 1.5) and test guidelines from Section 3 are covered. Subsequent revisions of this document will cover the transfer of similar information between the VC Integrator and the manufacturing Test Engineering function.

Virtual Component Transfer Specification
Version 2 (VCT 1 2.1)
Virtual Component Transfer DWG
Revision Date: January 2001
Released October 1999

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The VCT 1 2.1 Specification defines all the itemized documentation requirements that need to be transferred from the VC providers to the VC users along with the VC design data. VCT 1 2.1 clarifies what documentation is needed by the VC integrators and is required to be provided by the VC providers. Adequate documentation is absolutely essential if the mix and match of diverse VCs is to succeed. VC providers benefit from knowing exactly what is needed, and VC integrators can use this specification as acceptance criteria when they are about to obtain a VC from a VC provider.

System-Level Interface Behavioral Documentation Standard
Version 1 (SLD 1 1.0)
System-Level Design DWG
Revision Date: March 24, 2000
Released March 2000

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This System-Level Interface (SLIF) Standard provides a mechanism for ensuring the complete description of VC communication at various levels of abstraction. It enables the clean separation of a VC's behavior from its communication protocols, thereby easing the reuse of the same behavioral block with different interfaces. This standard also helps to ease the hand-off of system-level VC models between vendors and integrators, and provides a foundation to guide the import of VC models into different simulation and design environments. The SLIF standard will improve comprehension of VC interface behaviors at the system level, support block reuse through improved model generation, and link VC models at multi-levels of interface abstractions. The SLIF standard provides a structure to describe:

A core set of interface layer abstractions that must be delivered with a VC

• The method for specifying the interface layering principle adopted by the provider, (flexible)
• The structure for the description of each interface layer, and the definition of a behavioral syntax
• The link between the interface and the VC implementations or models
• A rigorous technique for specifying the hierarchical relationship between interface abstractions
  

Test Access Architecture Standard
Version 1 (TST 2 1.0)
Manufacturing-Related Test DWG
Revision Date: September 2001
Released September 2001

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This document describes a standard for manufacturing test access to individual virtual components (VCs) embedded in a System-on-a-Chip (SoC). Test access refers to the ability to apply test stimuli to an individual VC and to monitor the response of the individual VC as a result of the applied test stimuli. Without a standard for test access, SoC designers and users may have difficulty accessing the individual VCs that are integrated with other application circuitry on an SoC. This makes it difficult to test the interconnect and user-defined logic between the VCs, as well as the VCs themselves. This standard was conceived to support the use and reuse of previously generated test vectors for individual VCs. The necessary logical structures needed to support the reuse of previously generated test vectors for individual VCs are introduced and defined in this document.

Virtual Component Attributes (VCA) with Formats for Profiling, Selection and Transfer Standard
Version 2 (VCT 2 2.3)
Virtual Component Transfer DWG
Revision Date: March 2003
Released March 2001

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This document defines a set of attributes for the high-level profiling and characterization of virtual components (VCs). These attributes cover subjects such as function, performance claims, process compatibility, system and logic description, physical description, operating conditions, integration requirements, third-party support, and much more. Attribute definitions include detailed data type information and have a consistent structure. They are designed to facilitate the rapid and easy identification of desired VCs from catalogs and databases containing a large number and variety of VCs. Users depend on such catalog data when they search and select appropriate VCs for their applications. While it is neither practical nor sensible to standardize the formats and contents of proprietary catalog databases, the efficient and unambiguous exchange of catalog data requires definition and compliance with an industry accepted common format. VCT 2 2.3 achieves this objective by establishing a standard classification scheme for VC characteristics, and it imposes no requirements on the formats and structure used within any specific database. In order to meet the VCT 2 2.3 Standard, VC catalog providers need merely parse their proprietary formats into this common exchange format and include the documents and design data specified in Table 1 of the VSIA Deliverables Document.

Hard Intellectual IP (IP) Tagging Standard
Version 2 (IPP 1 2.0)
Intellectual Property Protection DWG
Release Date: June 2000
Revision Released: November 2006

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The VCID provides semiconductor foundries and providers of virtual components (VCs) with an automated and succinct means to track the use of VCs into the fabrication processes. This is accomplished by the use of tracking information embedded by VC providers or users into the Graphical Design System II-Stream (GDSII-Stream) file. This approach was based on a development from Artisan Components. This standard addresses only the tracking of VCs into the mask-making portion of the fabrication processes. It does not address protection of the Intellectual Property (IP) as a VC. The specified tracking mechanism is not secure. It is susceptible to tampering and is intended only to facilitate the passing, use and sharing of information among honest VC users and VC providers; it provides a ready means for surrounding infrastructure to be built.

Soft Intellectual Property (IP) Tagging Standard
Version 1.0 (IPP 4 1.0)
Intellectual Property Protection DWG
Released: August 2004
Revision Date: 2006

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Data Sheet

The soft-IP tagging standard provides rules and guidance to track non-hardened or soft IP throughout the entire design and development process, establishing critical identification and revision records from RTL down to the physical GDSII levels.

Virtual Component Interface Standard
Version 2 (OCB 2 2.0)
On-Chip Bus DWG
Revision Date: April 2001
Released March 2000

According to an agreement between VSIA and OCP International Partnership, OCP-IP has assumed stewardship of these specifications. For information about the VSIA OCB standard, please send an email to the OCP-IP organization at: admin@ocpip.org.

VSIA Architecture Document
Version 1.0
VSI Alliance
March, 1997

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This document presents the original baseline architecture for the VSIA proposed set of specifications. It was updated and replaced by the VSIA Overview Document and the VSIA Deliverables Document. The Deliverables Document is now available.

VSIA Deliverables Document
Version 2 (DD 2.6.0)
VSI Alliance
Revision May 2002

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This document summarizes VSIA specified deliverables, which are explained in detail in the individual specifications. The summary information is expressed in a Table, "VSIA Deliverables Summary." Appendix D. contains the VSIA Compliance Policy, which is the means for vendors to claim and show compliance to VSIA specifications for their products. This document is updated each time a VSIA specification is updated, and is therefore the central document indicating the current status of all released VSIA specifications. Those using the VSIA summary information need to study the VSIA specifications to understand the full meaning of the data.

Intellectual Property Protection White Paper: Schemes, Alternatives and Discussion  
Version 1 (IPPWP 1 1.1)
Intellectual Property Protection DWG
Revision Date: January 8, 2001
Released August 2000

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This paper identifies open, interoperable, standards-based solutions (or guidelines and information where standards are not practical) for VC protection which balances the level of security with customer usability of VCs, while fostering design reuse from creation to the effective use of VCs.

White Paper: The Value and Management of Intellectual Assets
Version 1.0 (IPPWP 2 1.0)
Intellectual Property Protection DWG
Revision Date: June 2002
Released June 2002

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This paper outlines methods used to establish a value for a firm’s intellectual property (IP). It describes how firms may manage their IP in order to maximize its value to the firm, whether by maximizing revenue or return on investment, or by maximizing the price that customers pay to license and use the IP.

Technical Measures and Best Practices for Securing Proprietary Information
Version 1.0 (IPPWP 3.1.0)
Intellectual Property Protection DWG
Revision Date: November 2002
Released November 2002

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The purpose of this document is to begin to define standards and best practices for securing intellectual property (IP) from external (outside the corporate perimeter) attacks and internal (inside the corporate perimeter) compromise. It covers protection for IP that is stored and for IP that is transported over data networks.

Platform-Based Design Taxonomy
Version 1 (PBD 11.0)
Platform-Based Design DWG
Member review ended December 12, 2003

The VSI Alliance taxonomies have been updated by several VSI Alliance members, and are now all offered within one book that will be published in early 2005. For more information, please go to http://edataxonomy.com/.

VSIA System Level Design Model Taxonomy Document
Version 2 (SLD 2 2.1)
System-Level Design DWG
Released July 2001

The VSI Alliance taxonomies have been updated by several VSI Alliance members, and are now all offered within one book that will be published in early 2005. For more information, please go to http://edataxonomy.com/.

Taxonomy of Functional Verification for Virtual Component Development and Integration
Version 1 (VER 1 1.2)
Functional Verification DWG
Released January 2001

The VSI Alliance taxonomies have been updated by several VSI Alliance members, and are now all offered within one book that will be published in early 2005. For more information, go to http://edataxonomy.com/.

VSIA QIP Metric version 4.0
VSI Alliance
Released June 2004

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With the announcement of the Quality Metric for IP, the VSI Alliance has addressed one of the toughest problems in the SoC industry: ensuring the quality of IP cores. We encourage VSI Alliance members and non-members to download this executable, self-scoring spreadsheet and apply it to a real IP core.

Hard IP Tag Reader/Writer
IP Protection
Released November 2006

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Tag Reader/Writer Data Sheet

The Tag IP Software (TIPS) donated to VSIA by Freescale enables users to utilize a common user interface to read and write tags into physical designs independent of the EDA tool used. The text tag information is maintained using an XML schema, easing the user interface and ensures that the tags are correct by construct. The software works in conjunction with the VSIA Hard IP Tagging Standard.